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RT7278 ? ds7278-00 january 2013 www.richtek.com 1 copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? 3a, 18v, 700khz acot tm synchronous step-down converter features z z z z z acot tm mode enables fast transient response z z z z z 4.5v to 18v input voltage range z z z z z 3a output current z z z z z 60m internal low site n-mosfet z z z z z advanced constant on-time control z z z z z support all ceramic capacitors z z z z z up to 95% efficiency z z z z z 700khz switching frequency z z z z z adjustable output voltage from 0.765v to 8v z z z z z adjustable soft-start z z z z z cycle-by-cycle current limit z z z z z input under voltage lockout z z z z z thermal shutdown z z z z z rohs compliant and halogen free applications z industrial and commercial low power systems z computer peripherals z lcd monitors and tvs z green electronics/appliances z point of load regulation for high-performance dsps, fpgas, and asics simplified application circuit general description the RT7278 is a synchronous dc/dc step-down converter with advanced constant on-time (acot tm ) mode control. it achieves high power density to deliver up to 3a output current from a 4.5v to 18v input supply. the proprietary acot tm mode offers an optimal transient response over a wide range of loads and all kinds of ceramic capacitors, which allows the device to adopt very low esr output capacitors for ensuring performance stabilization. in addition, RT7278 keeps an excellent constant switching frequency under line and load variation and the integrated synchronous power switches with the acot tm mode operation provides high efficiency in whole output current load range. cycle-by-cycle current limit provides an accurate protection by a valley detection of low side mosfet and external soft-start setting eliminates input current surge during startup. protection functions also include output under voltage protection, output over voltage protection, and thermal shutdown. marking information RT7278gsp : product number ymdnn : date code RT7278 gspymdnn en RT7278 pvcc fb gnd vin v in c1 c2 boot l1 c6 c7 sw ss c5 c4 v out r1 r2 c3 v pvcc enable
RT7278 2 ds7278-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. pin no. pin name pin function 1 en enable control input. a logic-high enables the converter; a logic-low forces the ic into shutdown mode reducing the supply current to less than 10 a. 2 fb feedback voltage input. it is used to r egulate the output of the converter to a set value via an external resistive vo ltage divider. the feedback threshold voltage is 0.765v typically. 3 pvcc regulator output for internal circuit. connect a 1 f capacitor to gnd to stabilize output voltage. 4 ss soft-start time setting. ss controls the soft-start period. connect a capacitor from ss to gnd to set the soft-start period. a 3.9nf capacitor sets the soft-start period of v out to 2.6ms. 5, 9 (exposed pad) gnd ground. the exposed pad should be sol dered to a large pcb and connected to gnd for maximum th ermal dissipation. 6 sw switch node. connect this pin to an external l-c filter. 7 boot bootstrap supply for high side gate driver. connect a 0.1 f or greater ceramic capacitor from boot to sw pins. 8 vin power input. the input voltage range is fr om 4.5v to 18v. must bypass with a suitably large ( 10 f x 2) ceramic capacitor. functional pin description pin configurations (top view) sop-8 (exposed pad) en fb pvcc ss vin boot gnd sw gnd 2 3 4 5 6 7 8 9 ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. RT7278 package type sp : sop-8 (exposed pad-option 2) lead plating system g : green (halogen free and pb free)
RT7278 3 ds7278-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. function block diagram ugate lgate driver sw boot pvcc switch controller on-time en fb comparator sw gnd internal regulator pvcc vibias v ref pvcc + - - 2a pvcc ripple gen. vin fb ss over current protection en operation in normal operation, the high side n-mosfet is turned on when the fb comparator sets the switch controller, and it is turned off when on-time controller resets the switch controller. while the high side n-mosfet is turned off, the low side n-mosfet is turned on and waits for the fb comparator to set the beginning of next cycle. the fb comparator sets the switch controller by comparing the feedback signal (fb) from output voltage with the internal 0.765v reference. when load transient induces vout drop, the fb voltage will be less than its threshold voltage. this means that the high side n-mosfet will turn on again immediately after minimum off-time expired. the switching frequency will vary during the transient period thus can provide a very fast transient response. after the load transient finished, the RT7278 will be back to steady state with a constant switching frequency. enable activate internal regulator once en input level is higher than the target level. force ic to enter shutdown mode when the en input level is lower than 0.4v internal regulator provide internal power for logic control and switch gate drivers. on-time controller control on-time according to vin and sw to obtain constant switching frequency.
RT7278 4 ds7278-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. (v in = 12v, t a = 25 c, unless otherwise specified) electrical characteristics recommended operating conditions (note 4) z supply voltage, vin ----------------------------------------------------------------------------------------------- 4.5v to 18v z junction temperature range ------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply voltage, vin ----------------------------------------------------------------------------------------------- ? 0.3v to 21v z switch voltage, sw ----------------------------------------------------------------------------------------------- ? 0.8v to (v in + 0.3v) <10ns ----------------------------------------------------------------------------------------------------------------- ? 5v to 25v z boot to sw , pvcc ---------------------------------------------------------------------------------------------- ? 0.3v to 6v z other pins voltage ------------------------------------------------------------------------------------------------- ? 0.3v to 21v z power dissipation, p d @ t a = 25 c sop-8 (exposed pad) -------------------------------------------------------------------------------------------- 2.041w z package thermal resistance (note 2) sop-8 (exposed pad), ja --------------------------------------------------------------------------------------- 49 c/w sop-8 (exposed pad), jc -------------------------------------------------------------------------------------- 15 c/w z junction temperature range ------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ----------------------------- ------------------------------------------- 260 c z storage temperature range ------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) --------------------------------------------------------------------------------------- 2kv parameter symbol test conditions min typ max unit supply current shutdown current i shdn v en = 0v -- 1.5 10 a quiescent current i q v en = 3v, v fb = 1v -- 0.7 -- ma logic threshold logic-high 2 -- 18 en input voltage logic-low -- -- 0.4 v v fb voltage and discharge resistance feedback threshold voltage v fb 4.5v v in 18v 0.757 0.765 0.773 v feedback input current i fb v fb = 0.8v ? 0.1 0 0.1 a v pvcc output v pvcc output voltage v pvcc 6v v in 18v, 0 < i pvcc < 5ma 4.7 5.1 5.5 v line regulation 6v v in 18v, i pvcc = 5ma -- -- 20 mv load regulation 0 < i pvcc < 5ma -- -- 100 mv output current i pvcc v in = 6v, v pvcc = 4v -- 110 -- ma
RT7278 5 ds7278-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. the pcb copper area of exposed pad is 70mm 2 . note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit r ds(on) high-side r ds(on)_h -- 90 -- switch on resistance low-side r ds(on)_l -- 60 -- m current limit current limit i lim 3.5 4.1 5.7 a thermal shutdown thermal shutdown threshold t sd -- 150 -- c thermal shutdown hysteresis t sd -- 20 -- c on-time timer control on-time t on v in = 12v, v out = 1.05v -- 145 -- ns minimum on-time t on(min) -- 60 -- ns minimum off-time t off(min) -- 230 -- ns soft-start ss charge current v ss = 0v 1.4 2 2.6 a ss discharge current v ss = 0.5v 0.05 0.1 -- ma uvlo uvlo threshold vin rising to wake up v pvcc 3.55 3.85 4.15 hysteresis -- 0.3 -- v
RT7278 6 ds7278-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. table 1. suggested component values v out (v) r1 (k ) r2 (k ) c3 (pf) l1 ( h) c7 ( f) 1 6.81 22.1 -- 1.4 22 to 68 1.05 8.25 22.1 -- 1.4 22 to 68 1.2 12.7 22.1 -- 1.4 22 to 68 1.8 30.1 22.1 5 to 22 2 22 to 68 2.5 49.9 22.1 5 to 22 2 22 to 68 3.3 73.2 22.1 5 to 22 2 22 to 68 5 124 22.1 5 to 22 3.3 22 to 68 7 180 22.1 5 to 22 3.3 22 to 68 typical application circuit en RT7278 pvcc fb gnd vin v in 10f x 2 c1 0.1f c2 boot l1 1.4h 0.1f c6 22f x 2 c7 sw ss 3.9nf c5 1f c4 v out 1.05v/3a 8.25k r1 22.1k r2 c3 v pvcc 8 1 5, 9 (exposed pad) 4 6 7 2 3 enable
RT7278 7 ds7278-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. typical operating characteristics output voltage v s. input voltage 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 4 5 6 7 8 9 10 11 12 13 14 15 16 17 input voltage (v) output voltage (v) v in = 4.5v to 17v, v out = 1.05v output voltage vs. temperature 1.00 1.02 1.04 1.06 1.08 1.10 -50-25 0 25 50 75100125 temperature (c) output voltage (v) v in = 12v, v out = 1.05v, i out = 0a efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) v in = 5v v in = 12v v in = 17v v out = 1.05v output voltage vs. output current 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 output current (a) output voltage (v) v out = 1.05v v in = 17v v in = 12v v in = 5v switching frequency vs. input voltage 650 660 670 680 690 700 710 720 730 740 750 4 6 8 1012141618 input voltage (v) switching frequency (khz) 1 v out = 1.05v, i out = 0.6a switching frequency vs. temperature 650 660 670 680 690 700 710 720 730 740 750 -50 -25 0 25 50 75 100 125 temperature (c) switching frequency (khz) 1 v out = 1.05v, i out = 0.6a
RT7278 8 ds7278-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. current limit vs. temperature 4.0 4.4 4.8 5.2 5.6 6.0 -50 -25 0 25 50 75 100 125 temperature (c) current limit (a) v in = 12v, v out = 1.05v time (1 s/div) output ripple voltage v lx (10v/div) v in = 12v, v out = 1.05v, i out = 3a v out (10mv/div) time (1 s/div) output ripple voltage v lx (10v/div) v in = 12v, v out = 5v, i out = 3a v out (10mv/div) time (250 s/div) load transient response v out (50mv/div) i out (2a/div) v in = 12v, v out = 1.05v, i out = 10ma to 3a time (100 s/div) load transient response v out (20mv/div) i out (2a/div) v in = 12v, v out = 1.05v, i out = 1a to 3a currrent limit vs. input voltage 4.0 4.4 4.8 5.2 5.6 6.0 4681012141618 input voltage (v) currrent limit (a) v out = 1.05v
RT7278 9 ds7278-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. time (1ms/div) power on from en v in = 12v, v out = 1.05v, i out = 3a v out (1v/div) v en (2v/div) i out (2a/div) time (10 s/div) power off from en v in = 12v, v out = 1.05v, i out = 3a v out (1v/div) v en (2v/div) i out (2a/div) time (5ms/div) power on from vin v in = 12v, v out = 1.05v, i out = 3a v out (1v/div) v in (5v/div) i out (2a/div) time (10ms/div) power off from vin v in = 12v, v out = 1.05v, i out = 3a v out (1v/div) v in (5v/div) i out (2a/div) en current vs. en voltage 0 1 2 3 4 5 6 7 8 9 10 024681012141618 en voltage (v) en current ( a) v in = 17v
RT7278 10 ds7278-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. to prevent enabling circuit when v in is smaller than the v out target value, a resistive voltage divider can be placed between the input voltage and ground and connected to the en pin to adjust ic lockout threshold, as shown in figure 3. for example, if an 8v output voltage is regulated from a 12v input voltage, the resistor r en2 can be selected to set input lockout threshold larger than 8v. application information the RT7278 is a synchronous high voltage buck converter that can support the input voltage range from 4.5v to 18v and the output current up to 3a. it adopts acot tm mode control to provide a very fast transient response with few external compensation components. pwm operation it is suitable for low external component count configuration with appropriate amount of equivalent series resistance (esr) capacitors at the output. the output ripple valley voltage is monitored at a feedback point voltage. the synchronous high side mosfet is turned on at the beginning of each cycle. after the internal on- time timer expires, the mosfet is turned off. the pulse width of this on-time is determined by the converter's input and output voltages to keep the frequency fairly constant over the entire input voltage range. advanced constant on-time control the RT7278 has a unique circuit which sets the on-time by monitoring the input voltage and sw signal. the circuit ensures the switching frequency operating at 700khz over input voltage range and loading range. soft-start the RT7278 contains an external soft-start clamp that gradually raises the output voltage. the soft-start timing can be programmed by the external capacitor between ss pin and gnd. the chip provides a 2 a charge current for the external capacitor. if a 3.9nf capacitor is used, the soft-start will be 2.6ms (typ.). the available capacitance range is from 2.7nf to 220nf. ss ss c5 (nf) 1.365 t (ms) = i (a) chip enable operation the en pin is the chip enable input. pulling the en pin low (<0.4v) will shut down the device. during shutdown mode, the RT7278 ' s quiescent current drops to lower than 10 a. driving the en pin high (>2v, <18v) will turn on the figure 1. external timing control an external mosfet can be added to implement digital control on the en pin when the en pin input voltage is lower than 2v, as shown in figure 2. in this case, a 100k pull-up resistor, r en , is connected between v in and the en pin. mosfet q1 will be under logic control to pull down the en pin. figure 2. digital enable control circuit figure 3. resistor divider for lockout threshold setting device again. for external timing control, the en pin can also be externally pulled high by adding a r en resistor and c en capacitor from the vin pin (see figure 1). RT7278 en gnd v in r en c en en RT7278 en gnd 100k v in r en q1 en RT7278 en gnd v in r en1 r en2
RT7278 11 ds7278-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. high frequency with small ripple current can achieve highest efficiency operation. however, it requires a large out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? input and output capacitors selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the high side mosfet. a low esr input capacitor with larger ripple current rating should be used for the maximum rms current. the rms current is given by : out in rms out(max) in out v v i = i 1 vv ? this formula has a maximum at v in = 2v out , where i rms = i out / 2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for the input capacitor, two 10 f and 0.1 f low esr ceramic capacitors are recommended. the selection of c out is determined by the required esr to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. the output ripple, v out , is determined by : output voltage setting the resistive divider allows the fb pin to sense the output voltage as shown in figure 4. under voltage lockout protection the RT7278 has under voltage lockout protection (uvlo) that monitors the voltage of pvcc pin. when the v pvcc voltage is lower than uvlo threshold voltage, the RT7278 will be turned off in this state. this is non-latch protection. over temperature protection the RT7278 equips an over temperature protection (otp) circuitry to prevent overheating due to excessive power dissipation. the otp will shut down switching operation when junction temperature exceeds 150 c. once the junction temperature cools down by approximately 20 c the main converter will resume operation. to keep operating at maximum, the junction temperature should be prevented from rising above 150 c. inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and an output voltage. the ripple current i l increases with higher v in and decreases with higher inductance. figure 4. output voltage setting the output voltage is set by an external resistive divider according to the following equation. it is recommended to use 1% tolerance or better divider resistors. ) out r1 v = 0.765(1 r2 + inductor to achieve this goal. for the ripple current selection, the value of i l = 0.2(i max ) will be a reasonable starting point. the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : out l out 1 viesr 8fc ?? ?? + ?? ?? the output ripple will be highest at the maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may need to meet the esr and rms current handling requirements. higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at input and gnd fb r1 r2 v out RT7278
RT7278 12 ds7278-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. figure 5. external bootstrap diode pvcc capacitor selection decouple with a 1 f ceramic capacitor. x7r or x5r grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. over current protection when the output shorts to ground, the inductor current decays very slowly during a single switching cycle. an over current detector is used to monitor inductor current to prevent current runaway. the over current detector monitors the voltage between sw and gnd during the low side mosfet turn-on state. this is cycle-by-cycle protection. the over current detector also supports temperature compensated. output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. external bootstrap diode connect a 0.1 f low esr ceramic capacitor between the boot and sw pins. this capacitor provides the gate driver voltage for the high side mosfet. it is recommended to add an external bootstrap diode between an external 5v and the boot pin for efficiency improvement when input voltage is lower than 5.5v or duty ratio is higher than 65%. the bootstrap diode can be a low cost one, such as 1n4148 or bat54. the external 5v can be a 5v fixed input from system or a 5v output of the RT7278. note that the external boot voltage must be lower than 5.5v thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for sop-8 (exposed pad) package, the thermal resistance, ja , is 49 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formulas : p d(max) = (125 c ? 25 c) / (49 c/w) = 2.041w for sop-8 (exposed pad) package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 6 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 6. derating curve of maximum power dissipation 0.0 0.5 1.0 1.5 2.0 2.5 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb sw boot 5v RT7278 0.1f
RT7278 13 ds7278-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. figure 7. pcb layout guide layout consideration follow the pcb layout guidelines for optimal performance of the RT7278 ` keep the traces of the main current paths as short and wide as possible. ` put the input capacitor as close as possible to the device pins (vin and gnd). en fb pvcc ss vin boot gnd sw gnd 2 3 4 5 6 7 8 9 c2 c1 c6 l1 v out c7 v out c4 c5 r1 r2 gnd input capacitor must be placed as close to the ic as possible. sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. the resistor divider must be connected as close to the device as possible. ` sw node is with high frequency voltage swing and should be kept at small area. keep sensitive components away from the sw node to prevent stray capacitive noise pickup. ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the RT7278 feedback pin. ` the gnd and exposed pad should be connected to a strong ground plane for heat sinking and noise protection.
RT7278 14 ds7278-00 january 2013 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138 outline dimension

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